1. Field of the Invention
The present invention relates to a semiconductor device which uses bumps formed of solder balls or the like as external connection terminals, and more particularly to a semiconductor device that is enhanced in the breakdown voltage to electrostatic noise.
2. Description of the Prior Art
In the semiconductor devices (referred to as LSIs hereinafter) of recent years, the increase in the number of pins used is remarkable along with the achieved high level of integration and scale, as a result of advancement in the micro processing technology. As the methods of making the increase in the number of pins and miniaturization of the LSIs compatible, flip chip type LSIs (referred to as FCLSIs hereinafter), CSP (chip size package/chip scale package) type LSIs, and the like, in which bumps for external connection are formed two-dimensionally on the main face side where semiconductor chip elements are formed via an insulating resin layer, an interposer, or the like, have been developed. In addition, as another method for making the increasing pin number and the miniaturization compathatible, there have been developed the ball grid array (BGA) type LSIs. In this method, a semiconductor chip is mounted on the face opposite to the bump formation face of a printed board where bumps of solder ball or the like are arranged two-dimensionally, then after bonding a wiring conductor of the printed board connected to each bump to an electrode on the semiconductor chip with a wire of metal such as gold (Au), or solder connecting the electrode on the semiconductor chip with a bump formed thereon to the wiring conductor on the printed board, the semiconductor chip on the printed board and bonding wires and the like are sealed with a resin.
In FIG. 7 which shows an example of the conventional FCLSIs, part (a) is a plan view showing schematically the arrangement state of ball bumps on the face on which ball bumps are formed, and part (b) is an enlarged plan view of the portion including the connection wirings between the ball bumps and the electrodes on the chip in part C of part (a), and FIG. 8 is a sectional view along line P2–P2′ in part (a). Referring to FIG. 7 and FIG. 8, it can be seen that a conventional FCLSI 500 is provided with external connection bumps 521 and 523 formed two-dimensionally, via an insulating resin layer 515, on its main face where elements of a semiconductor chip 510 are formed, and rewiring conductors 541 which connect respective bumps 521 and 523 to respective electrodes 513 of the semiconductor chip 510.
Moreover, in FIG. 9 which shows an example of the conventional BGA type LSIs, (a) is a plan view of the back face where ball bumps are formed, and (b) and (c) are sectional views along line P3–P3′ of (a), showing the cases in which the electrodes of the semiconductor chip and the wiring conductors on the printed board are connected by bondings of metal wire and by bumps, respectively. Referring to FIG. 9, a conventional BGA type LSI 600 has a semiconductor chip 610 or 630 mounted on one main face of a printed board 602, first bump electrodes 620 of solder or the like formed at openings of an insulating film 607 formed on the face opposite to the one main face of the printed board 602, board wirings 604 and the chip 610 or 630 are connected either by bondings of metal wire 606 or by second bump electrodes 632 formed on the chip 630, and the semiconductor chip 610 and the metal wires 606 or the semiconductor chip 630 and the second bump electrodes 632 formed thereon are covered with a sealing resin 608.
In the FCLSI, CSP type LSI, BGA type LSI, and the like, the problems related to the increasing pin number and the miniaturization of the LSI are simultaneously taken care of by arranging the bumps that serve as external connection electrodes in two dimensions. In connection with these LSIs, installment of dummy bumps (referred to as DBPs hereinafter) is disclosed in, for example, Japanese Patent Applications Laid Open, No. Hei 1-238148 (referred to as well-known example 1 hereinafter) and Japanese Patent Applications Laid Open, No. Hei 10-12620 (referred to as well-known example 2 hereinafter) in order to increase the connection strength at mounting on the mount substrate as well as to enhance the connection reliability by securing parallel holding of the LSI and the mount substrate through uniformization of bump arrangement within the bump formation plane of the LSI, although it is not necessarily indispensable for realization of the functions of the LSIs.
In FIG. 10 for describing the semiconductor chip disclosed in well-known example 1, (a) and (b) are a plan view showing the arrangement of the bump electrodes and a sectional view of an important part of the chip, respectively, and (c) and (d) are schematic sectional views showing sequentially the mounting processes as seen at a position corresponding to line P4–P4′ in (a), respectively. Referring to FIG. 10, a semiconductor chip 701 disclosed in the well-known example 1 has, in its central section, bump electrodes 702 for connecting circuit elements in the chip to wiring conductors of a support substrate 709 to be mounted, and has DBPs 703 provided, at nearly a constant interval, in the periphery of the chip 701 surrounding the bump electrodes 702. The bump electrodes 702 and the DBPs 703 are formed in a manner stated roughly as in the following. On a first wiring conductor 731 which makes contact with an element region 711 of the chip 701 at an opening of an oxide film 721, a second wiring conductor 732 is formed via a layer insulating film 722, making contact with the first wiring conductor 731 at an opening in the layer insulating film 722. A passivation film 708 is formed to cover the top faces of the second wiring conductor 732 and the layer insulating film 722, and openings are formed on the second wiring conductor 732 and near the outer periphery of the chip 701 by photoetching. Then, after formation of an underlying metal layer 707 by laminating a chromium (Cr), a copper (Cu) and a gold (Au) films, the layer is patterned by photoetching, solder spots are attached onto the underlying metal layer 707 by solder plating, and solder spots are made spherical by heating to about 350° C., forming bump electrodes 702 and somewhat larger DBPs 703. At mounting of the chip 701, the bump formation face of the chip 701 is placed on the wiring support substrate 709, opposing the surface of the substrate 709. In this case, a thickness supplementing solder layers 710 are attached on the substrate in advance to compensate for the height difference between the DBPs 703 and the bump electrodes 702. When the system is subjected to solder reflow thereafter, the bump electrodes 702 with small diameter melt first to be adhered to the supplementary solder layers 710 during which time the bump electrodes 702 are formed into solder posts with height equal to the distance between the chip and the substrate that is kept constant by the DBPs with largediameter. After lapse of a certain time, the DBPs 703 start to melt and the peripheral part of the chip 701 and the substrate 709 are bonded. Following that, the DBPs 703 are fixed to the substrate 709 by covering their surroundings with, for example, an epoxy resin 704.
FIG. 11 is the plan view showing an example of configuration of bump electrodes of an FCLSI disclosed in the well-known example 2. The bump electrodes of the FCLSI 750 consist of a main bump electrode line 752a which is connected to the elements within the chip and a dummy auxiliary bump electrode line 752b which is not connected to the elements within the chip, and these are arranged along the periphery of the chip with the auxiliary bump electrode line 752b on the outer peripheral side. Moreover, the diameter of the bump electrodes in the auxiliary bump electrode line 752b is made larger than the diameter of the bump electrodes in the main bump electrode line 752a in order to facilitate filling of the resin between the chip and the substrate through increase in the amount of solder per chip and to enhance the bonding life of bump electrodes that are further away from the center of the chip.
However, it became clear with the configuration of the semiconductor chip as disclosed in well-known examples 1 and 2 that when electrostatic noise is applied to the DBPs, there arises a problem in that discharge is caused between the neighboring bump electrodes, and the internal elements connected to the bump electrodes are damaged or broken down.
More specifically, when there exist externally connected electrodes, like the DBPs in this case, that are not connected to any of the elements within the semiconductor chip, and electrostatic noise is applied to the DBPs, it results in a gap discharge phenomenon due to absence of discharge route for the charge. Moreover, since the voltage in the gap discharge phenomenon is higher in the case of an FCLSI, CSP type LSI, BGA type LSI, or the like where the bump electrode space (pin space) is larger than that in the case of a supermultiple-pin quad flat package (QFP) or the like where the pin space is smaller, damages to the adjacent bump electrodes are more conspicuous accordingly.
For example, in the chip 701 of the well-known example 1, the bump electrodes 702 adjacent to the DBPs 703 are connected to an electrostatic discharge protection circuit (not shown) formed on the semiconductor chip 701 via the first wiring conductor 731 and the second wiring conductor 732. Since, however, the electrostatic noise due to the gap discharge phenomenon is a pulse steeper than the breakdown voltage of the electrostatic discharge protection circuit, there is a possibility that it breaks down the semiconductor chip.
The gap discharge phenomenon is described in detail in, for example, Technical Research Report of the Institute of Electronics, Information and Communication Engineers (Environmental Electromagnetic Engineering), Dec. 18, 1998, pp. 37–42. According to the paper, the discharge is a very steep pulse with the current rise time of less than ins for voltages below 3,000V. On the other hand, according to the ESDA specifications, the JEDEC specifications, or the like used as the reference for the breakdown voltage in the design of normal LSI devices, the rise time of the discharge waveform is defined to be about 2–10 ns. The problem mentioned above is brought about because this value is gentle compared with the rise time of the discharge waveform in the gap discharge.
As the methods of resolving such a problem, a method of, for example, providing an electrostatic discharge protection circuit exclusively for external connection electrodes not connected to any of the elements within the semiconductor chip, namely, exclusively for non-connected (NC) pins, is disclosed in Japanese Patent Applications Laid Open, No. Hei 11-163247 (referred to as well-known example 3 hereinafter), although it is intended for dealing with a lead frame such as a QFP. In addition, a method of connecting dummy pins being NC pins to an adjacent input terminal via a resistor is disclosed in Japanese Patent Applications Laid Open No. Hei 11-233777 (referred to as well-known example 4 hereinafter).
FIG. 12 is an explanatory drawing of NC pins and the electrostatic discharge protection circuit disclosed in the well-known example 3. Referring to FIG. 12, there is shown a semiconductor device in which a bonding pad 812 and an electrostatic discharge protection circuit 814 dedicated to an NC pin are formed on a semiconductor chip 810, and an NC pin P1 (inner lead 803) and the bonding pad 812 dedicated to the NC pin are connected by a bonding wire 807. In this case, a method of preventing breakdown of the semiconductor chip due to electrostatic discharge to the input pins P3 adjacent to the NC pin P1 is disclosed by absorbing the overvoltage of the electrostatic noise applied to the NC pin P1 by the electrostatic discharge protection circuit 814 dedicated to the NC pin, and discharging (through surge path SGP) the charge to a power supply (Vcc, for example) line.
This method is effective in the point that the breakdown of the semiconductor chip 810 due to electrostatic discharge to the input pins P3 adjacent to the NC pin P1 is prevented by discharging the electrostatic noise applied to the NC pin P1 to the power supply line.
However, since the bonding pad 812 and the electrostatic discharge protection circuit 814 dedicated to the NC pin are formed in this method, the chip size becomes large as the number of the NC pins increases and the number of effective chips per semiconductor wafer decreases, so that it gives rise to the problem of increase in the production cost.
Moreover, in the well-known example 4, a method is disclosed in which the dummy terminal is connected to an adjacent input terminal via a resistor section, and a large quantity of static electricity generated in the dummy terminal is attenuated by the resistor section and the result is made to be absorbed by a protective circuit connected to the input terminal, or when a larger quantity of static electricity is generated, the protective circuit or internal TFT elements that are connected to the input terminals are protected by disconnecting the resistor section. However, it is also necessary in this method to provide a resistor for each NC pin which requires the chip size to be increased, so that similar to the well-known example 3, the number of effective chips per semiconductor wafer, leading to the problem of increase in the production cost.
Moreover, the problem relating to the electrostatic noise will not arise if the DBPs of the semiconductor device in the well-known examples 1 and 2 are connected to a power supply wiring such as the ground potential. However, it will result in a problem that the lead-out of the wiring conductors connected to the bump electrodes for signals on the mounting substrate becomes difficult. FIG. 13 shows drawings for describing the problem, which consists of a plan view of the electrodes and a wiring pattern of a mounting substrate 900 to be connected to external connection bumps of an FCLSI 500 when, for example, the FCLSI 500 in FIG. 5 is mounted on the mounting substrate 900, and a schematic enlarged plan view of the portion corresponding to portion B of the FCLSI 500. If DBPs 523a and DBPs 523b of the FCLSI 500 are connected to, for example, the ground potential within the FCLSI 500, the wiring patterns connected respectively to corresponding electrodes 923a and electrodes 923b of the mounting substrate 900 are also connected to the ground potential. If it is assumed that the number of passable wirings between electrodes in the mount substrate 900 is two, for example, the number of wirings between one pitch of the electrodes that can be led out to the outside from the mounting region of the FCLSI is three, including the one for the outermost peripheral electrode. However, when the outermost peripheral electrode is a DBP connected to a fixed potential such as the ground potential, the number that can be l;ed out as the signal lines is only two. Accordingly, when the outermost peripheral electrode is a DBP connected to a fixed potential such as the ground potential, the number of signal lines that can be led out to the outside from the mounting region of the FCLSI 500 is reduced, so that the number of BPs for signal that can be available for input/output of signals among the bumps of the FCLSI 500 is reduced, which becomes an especially serious problem in a signal processing LSI or the like needed for a large number of signal terminals.
Furthermore, the problems related to the LSI or the semiconductor chip disclosed in the well-known example 1 or the well-known example 2 will become more serious because of the anticipation that the bump electrode space will be reduced further with a further advancement in miniaturization and increase in the pin number of the future LSIs.